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low profile, 500 ma, 6 mhz, synchronous, step-down, dc-to-dc converter adp2125 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features 1.26 v fixed output voltage clock signal enable 6 mhz (maximum) operating frequency 500 ma continuous output current input voltage: 2.1 v to 5.5 v 0.3 a (typical) shutdown supply current compatible with tiny multilayer inductors internal synchronous rectifier internal compensation internal soft start output-to-ground short-circuit protection current-limit protection undervoltage lockout thermal shutdown protection ultrasmall, 0.405 mm height (maximum), 6-ball bumped_chip applications mobile phones digital still/video cameras digital audio portable equipment camera modules image stabilization systems general description the adp2125 is a high frequency, step-down, dc-to-dc converter optimized for portable applications in which board area and battery life are critical constraints. fixed frequency operation at 6 mhz enables the use of tiny ceramic inductors and capacitors. additionally, the synchronous rectification improves efficiency and results in fewer external components. over all load currents, the device uses a voltage regulating pulse-width modulation (pwm) mode that maintains a constant frequency with excellent stability and transient response. the adp2125 is enabled by a 6 mhz to 27 mhz external clock signal applied to the extclk pin. when the external clock is not switching and in a low state (extclk 0.5 v), the input is disconnected from the output and draws less than 0.3 a (typical) from the source. the adp2125 has an input voltage range of 2.1 v to 5.5 v, allowing the use of single li+/li polymer cell, three-cell alkaline, nimh cell, and other standard power sources. the adp2125 is internally compensated to minimize external components and can source up to 500 ma. other key features such as cycle-by-cycle peak current limit, soft start, undervoltage lockout (uvlo), output-to-ground short-circuit protection, and thermal shutdown provide protection for internal and external circuit components. typical application circuit a2 c2 b2 a1 b1 c1 vin gnd fb sw extclk nc nc = no connect off on c in 2.2f c out 4.7f input voltage 2.1v to 5.5v l 1.5h adp2125 output voltage 1.26v 08774-002 figure 1.
adp2125 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical application circuit ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing diagram ........................................................................... 4 ? absolute maximum ratings ............................................................ 5 ? thermal considerations .............................................................. 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 10 ? overview ..................................................................................... 10 ? external clock (extclk) enable ........................................... 10 ? internal control features .......................................................... 10 ? protection features .................................................................... 11 ? timing constraints .................................................................... 11 ? applications information .............................................................. 12 ? inductor selection ...................................................................... 12 ? input capacitor selection .......................................................... 12 ? output capacitor selection ....................................................... 13 ? thermal limit calculations ...................................................... 13 ? pcb layout guidelines .................................................................. 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 9/10revision 0: initial version
adp2125 rev. 0 | page 3 of 16 specifications v in = 3.6 v, v out = 1.26 v, t a = 25c for typical specifications, and t a = t j = ?40c to +85c for minimum and maximum specifications, unless otherwise noted. all specifications at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. typical specifications are not guaranteed. table 1. parameter symbol test conditions/comments min typ max unit supply operating input voltage range v in 2.1 5.5 v quiescent current no load 8 ma shutdown current v extclk = 0 v, open-loop 0.3 1.5 a undervoltage lockout rising v in threshold 1.9 2.1 v falling v in threshold 1.5 1.8 v output continuous output current 1 i load v in = 2.1 v to 5.5 v 500 ma output accuracy 2 v out v in = 2.3 v to 4.8 v v out ? 2% v out + 2% v fb bias current v fb = 1.2 v 4 9 a fb pull-down resistance r dschg v extclk = 0 v, i fb = 10 ma 110 180 switching characteristics pmos on resistance 180 340 m nmos on resistance 250 m sw leakage current v sw = 0 v, v in = 5.5 v 10 a pmos switch current limit open-loop 770 1000 1291 ma oscillator frequency f sw 4.83 5.52 6 mhz short-circuit protection rising v out threshold 0.55 0.7 v falling v out threshold 0.4 0.52 v extclk input high threshold voltage v extclk(h) v in = 2.5 v to 4.4 v 1.4 v low threshold voltage v extclk(l) v in = 2.5 v to 4.4 v 0.5 v leakage current v in = 5.5 v, v extclk = 2.1 v to 5.5 v 0.01 1 a duty cycle operating range d extclk 40 60 % frequency operating range f extclk 6 27 mhz thermal shutdown thermal shutdown threshold 146 c thermal shutdown hysteresis 13 c timing see figure 2 vin high to extclk on 1 t 1 v in = 2.1 v to 5.5 v 200 s extclk on to v out rising t 2 d extclk = 40% to 60%, f extclk = 6 mhz 17 23 32 s d extclk = 40% to 60%, f extclk = 27 mhz 16 21 28 s v out power-up time (soft start) 1 t 3 c out = 4.7 f, r load = 3.6 105 200 s extclk off to v out falling t 5 d extclk = 40% to 60%, f extclk = 6 mhz to 27 mhz 4.1 11 s v out power-down time t 6 c out = 4.7 f, r load = 3.6 36 s c out = 4.7 f, no load 1070 s minimum shutdown time 1 t 5 + t 6 c out = 4.7 f, no load 1400 s minimum power-off time 1 t 7 500 s 1 guaranteed by design. 2 transients not included in vo ltage accuracy specifications.
adp2125 rev. 0 | page 4 of 16 timing diagram t 6 t 7 t 5 t 3 t 2 t 1 v out(nom) 10% v in 10% v in 90% vin v out extclk 08774-003 figure 2. i/o timing diagram
adp2125 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating vin to gnd ?0.3 v to +6 v extclk to gnd ?0.3 v to +6 v sw, nc to gnd ?0.3 v to vin fb (vin 3.6 v) to gnd ?0.3 v to +3.6 v fb (vin < 3.6 v) to gnd ?0.3 v to vin operating ambient temperature (t a ) C40c to +85c 1 operating junction temperature (t j ) at i load = 500 ma C40c to +125c soldering conditions jedec j-std-020 1 the maximum operating junction temperature (t j(max) ) supersedes the maximum operating ambient temperature (t a(max) ). see the thermal considerations section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. thermal considerations the maximum operating junction temperature (t j(max) ) supersedes the maximum operating ambient temperature (t a(max) ) because the adp2125 can be damaged when the junction t emperature limits are exceeded. monitoring ambient tempera ture does not guarantee that t j is within the specified tem perature limits. in applications with high power dissipation and poor pcb thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and good pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the operating junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). t j is calculated using the following formula: t j = t a + ( p d ja ) (1) see the applications information section for further infor- mation on calculating the operating junction temperature for a specific application. thermal resistance ja of the package is based on modeling and calculation using a 4-layer board. ja is highly dependent on the application and board layout. in applications where high maximum power dissi- pation exists, attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. ja is specified for worst-case conditions, that is, a device soldered on a circuit board for surface-mount packages. ja is determined according to jedec standard jesd51-9 on a 4-layer printed circuit board (pcb). table 3 . thermal resistance package type ja unit 6-ball bumped bare die, 4-layer board 120 c/w esd caution
adp2125 rev. 0 | page 6 of 16 pin configuration and fu nction descriptions nc vin sw fb gnd 08774-005 1 a b c 2 ball a 1 indicator extclk top view ball side down bumps on opposite side (not to scale) figure 3. pin configuration table 4 . pin function descriptions pin no. mnemonic description a1 nc no connection. any voltage applied to this pin must be between gnd and vin. voltages above vin or below gnd exceed the absolute maximum ratings and may cause damage to the part. b1 sw switch node. c1 fb feedback divider input. connect the output capacitor fr om fb to gnd to set the output voltage ripple and to complete the control loop. a2 vin power supply input. b2 extclk external clock enable signal. the adp2125 powers up when a clock signal (6 mhz to 27 mhz) is detected on this pin. c2 gnd ground.
adp2125 rev. 0 | page 7 of 16 typical performance characteristics v in = 3.6 v, f extclk = 10 mhz, v out = 1.26 v, l = 1.8 h (700 ma, 0603 package, lqm18pn1r8nc0), c in = 2.2 f (6.3 v, 0402 package, x5r, grm155r60j225me15), c out = 4.7 f (4 v, 0402 package, x5r, grm155r60g475me47), and t a = 25c, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 efficiency (%) load current (ma) v in = 2.1v v in = 2.7v v in = 3.6v v in = 4.8v v in = 5.5v 08774-104 figure 4. efficiency vs. load current 90 85 80 75 70 65 60 2.1 5.1 4.6 4.1 3.6 3.1 2.6 efficiency (%) input voltage (v) i load = 100ma i load = 250ma i load = 500ma 08774-105 figure 5. efficiency vs. input voltage 11 10 9 8 7 6 5 4 2.1 5.1 4.6 4.1 3.6 3.1 2.6 quiescent current (ma) input voltage (v) t a = ?40c t a = +25c t a = +85c 08774-106 figure 6. quiescent current vs. input voltage 1.263 1.262 1.261 1.260 1.259 1.258 1.257 1 10 100 1000 output voltage (v) load current (ma) v in = 2.1v v in = 2.7v v in = 3.6v v in = 4.8v v in = 5.5v 08774-107 figure 7. output voltage accuracy 1.262 1.261 1.260 1.259 1.258 1.257 1.256 1.255 1 10 100 1000 output voltage (v) load current (ma) t a = ?40c t a = +25c t a = +85c 08774-108 figure 8. output voltage accuracy over temperature 2.1 5.1 4.6 4.1 3.6 3.1 2.6 0.9 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 shutdown current (a) input voltage (v) t a = ?40c t a = +25c t a = +85c sw = open 08774-109 figure 9. shutdown current vs. input voltage
adp2125 rev. 0 | page 8 of 16 2.1 5.1 4.6 4.1 3.6 3.1 2.6 350 300 250 200 150 100 p-channel r dson (m ? ) input voltage (v) t a = ?40c t a = +25c t a = +85c i sw = 500ma 08774-110 figure 10. pmos drain-to-source on resistance 2.1 5.1 4.6 4.1 3.6 3.1 2.6 450 400 350 300 250 200 150 n-channel r dson (m ? ) input voltage (v) t a = ?40c t a = +25c t a = +85c i sw = 500ma 08774-111 figure 11. nmos drain-to-source on resistance 2.1 5.1 4.6 4.1 3.6 3.1 2.6 6.0 5.8 5.6 5.4 5.2 5.0 frequency (mhz) input voltage (v) t a = ?40c t a = +25c t a = +85c 08774-112 figure 12. switching frequency vs. input voltage 1 2 load current (200ma/div) time (20s/div) output voltage (20mv/div) 1.26v offset v in = 2.1v v out = 1.26v 08774-113 figure 13. load transient response, 250 ma to 420 ma, v in = 2.1 v 1 2 load current (200ma/div) time (20s/div) output voltage (50mv/div) 1.26v offset v in = 3.6v v out = 1.26v 08774-114 figure 14. load transient response, 250 ma to 420 ma, v in = 3.6 v 1 2 load current (200ma/div) time (20s/div) output voltage (50mv/div) 1.26v offset v in = 5.5v v out = 1.26v 08774-115 figure 15. load transient response, 250 ma to 420 ma, v in = 5.5 v
adp2125 rev. 0 | page 9 of 16 1 2 3 inductor current (200ma/div) extclk (5v/div) time (20s/div) output voltage (500mv/div) v in = 3.6v v out = 1.26v no load 08774-116 figure 16. startup, no load 1 2 3 inductor current (200ma/div) extclk (5v/div) time (20s/div) output voltage (500mv/div) v in = 3.6v v out = 1.26v r load = 3.6 ? 08774-117 figure 17. startup, r load = 3.6 1 2 inductor current (1a/div) time (200s/div) output voltage (200mv/div) 08774-118 figure 18. output short-circuit response 1 2 3 time (100ns/div) output voltage (10mv/div) 1.26v offset inductor current (200ma/div) switch pin voltage (5v/div) 08774-119 v in = 3.6v figure 19. standard operation
adp2125 rev. 0 | page 10 of 16 theory of operation shoot- through control logic and pwm control thermal shutdown soft start bandgap bg fb bg agnd r1 fb r2 v out agnd agnd fb 6mhz oscillator b2 threshold detect v out discharge clk detect short-circuit protection compensation eamp r dschg 110 ? ramp v(v in ) zxcomp pilim pdrive pwm comp pv in c in 2.2f v in 2.1v to 5.5v av in ndrive pref c out 4.7f v out 1.26 v l 1.5h pgnd vin gnd sw agnd nref extclk on off c2 b1 a2 c1 gnd to v in a1 nc 08774-006 figure 20. internal block diagram overview the adp2125 is a high efficiency, synchronous, step-down, dc-to-dc converter that operates from a 2.1 v to 5.5 v input voltage. it provides up to 500 ma of continuous output current at a fixed output voltage. the 6 mhz operating frequency enables the use of tiny external components. the internal control schemes of the adp2125 give excellent stability and transient response. other internal features such as cycle-by- cycle peak current limiting, soft start, undervoltage lockout, output-to-ground short-circuit protection, and thermal shutdown provide protection for internal and external circuit components. external clock (extclk) enable the adp2125 is enabled by a 6 mhz to 27 mhz clock signal applied to the extclk pin (see figure 2 and figure 20 ). the adp2125 internally detects the clock signal and allows the converter to power up and the output voltage to rise to its nominal value. the adp2125 can detect a nonswitching state and disable the part whether the extclk gates low or high. if the extclk signal gates low, the part is shut down, reducing the current consumption to 0.3 a (typical). internal control features pulse-width modulation (pwm) pwm forces the part to maintain a fixed frequency of 6 mhz (maximum) over all load conditions. the adp2125 uses a hybrid proprietary voltage mode control scheme to control the duty cycle over load current and line voltage variation. this control provides excellent stability, transient response, and output regulation. synchronous rectification in addition to the p-channel mosfet switch, the adp2125 includes an n-channel mosfet switch to build the synchron- ous rectifier. the synchronous rectifier improves efficiency, especially for small load currents, and reduces cost and board space by eliminating the need for an external rectifier. soft start to prevent excessive input inrush current at startup, the adp2125 operates with an internal soft start. when extclk begins to oscillate, or when the part recovers from a fault (uvlo, tsd, or scp), a soft start timer begins. during this time, the peak current limit is gradually increased to its maximum. the output
adp2125 rev. 0 | page 11 of 16 t limit remains at to operate. es nt power components during certain faults e et still allows the converter to recover if the fault is removed. voltage increases in stages to ensure that the converter is able to start up effectively and in proper sequence. after the soft start period expires, the peak pmos switch curren 1 a (typical) and the part is able protection featur overcurrent protection to ensure that excessively high currents do not damage the inductor, the adp2125 incorporates cycle-by-cycle overcurre protection. this function is accomplished by monitoring the instantaneous peak current on the power pmos switch. if this current exceeds the pmos switch current limit (1 a typical), then the pmos is immediately turned off. this minimizes the potential for damage to and transient events. output short-circuit protection (scp) if the output voltage is shorted to gnd, a standard dc-to-dc controller delivers maximum power into that short. this may result in a potentially catastrophic failure. to prevent this, th adp2125 senses when the output voltage is below the scp threshold (typically 0.55 v). at this point, the controller turns off for approximately 450 s and then automatically initiates a soft start sequence. this cycle repeats until the short is removed or the part is disabled. figure 18 shows this operating behavior of the adp2125 during a short-circuit fault. the scp dramati- cally reduces the power delivered into the short circuit, y thermal shutdown (tsd) protection the adp2125 also includes tsd protection. if the die tempera- ture exceeds 146c (typical), th e tsd protection activates and turns off the power devices. they remain off until the die temperature falls 13c (typical), at which point the converter restarts. undervoltage lockout (uvlo) if the input voltage is below the uvlo threshold, the adp2125 automatically turns off the power switches and places the part in a low power consumption mode. this prevents potentially erratic operation at low input voltages. the uvlo levels have approximately 100 mv of hysteresis to ensure glitch-free startup. timing constraints shutdown time when the adp2125 enters shutdown mode after the extclk signal is removed, the adp2125 must remain in shutdown for a minimum of 1400 s, if no load is applied, before the extclk signal can be reapplied. this allows all internal nodes to discharge to an off state. power-off time when v in drops, thereby triggering uvlo, the adp2125 has a minimum power-off time (t 7 ) of 500 s that must elapse before v in can be reapplied. this allows all supplies to discharge enough power so that all internal devices are in an off state. t 7 v in 10% 08774-021 figure 21. power-off time
adp2125 rev. 0 | page 12 of 16 applications information the adp2125 is designed to be compatible with chip inductors and multilayer ceramic capacitors that are ideal for their small footprint and low height. the recommended components for this application may change as this technology advances. table 5 , table 6, and table 7 list compatible inductors and capacitors. this section describes the selection of external components. the component value ranges are limited to optimize efficiency and transient performance while maintaining stability over the full operating range. inductor selection the high switching frequency of the adp2125 allows for minimal output voltage ripple, even with small inductors. inductor sizing is a trade-off between efficiency and transient response. a small value inductor leads to a larger inductor current ripple that provides excellent transient response, but degrades efficiency. a small footprint and low height chip inductor can be used for an overall smaller solution size but has a higher dc resistance (dcr) value and lower current rating that can degrade performance. shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (emi). the recommended inductor for the adp2125 is 1.5 h. the inductor peak-to-peak current ripple, i l , can be calculated as follows: ( ) sw in out in out l flv vvv i ? = (2) it is important that the inductor be capable of handling the maximum peak inductor current, i pk , determined by the following equation: i pk = i load(max) + i l /2 (3) the dc current rating of the inductor should be greater than the calculated i pk to prevent core saturation. input capacitor selection the input capacitor must be rated to support the maximum input operating voltage. higher value input capacitors reduce the input voltage ripple caused by the switch currents on the vin pin. maximum rms input current for the application can be calculated using the following equation: () in out in out max load cin max rms v vvv i i ? = )( )(_ (4) place the input capacitor as close as possible to the vin pin to minimize supply noise. in principle, different types of capacitors can be considered, but for battery-powered applications, the best choice is the multi- layer ceramic capacitor, due to its small size, low equivalent series resistance (esr), and low equivalent series inductance (esl). it is recommended that the vin pin be bypassed with a 2.2 f input capacitor. the input capacitor can be increased without any limit for better input voltage filtering. x5r or x7r dielectrics with a voltage rating of 6.3 v or higher are recommended. table 5. inductor selection manufacturer series inductance (h) dcr (m) (typ) current rating (ma) size (l w h) (mm) package murata lqm18pn1r8nc0l 1.80 240 700 1.60 0.80 0.55 0603 lqm18pn1r5nb0l 1.50 350 600 1.60 0.80 0.40 0603 taiyo yuden ckp1608l1r5m 1.50 220 700 1.60 0.80 0.55 0603 table 6. input capacitor selection manufacturer part number capacitance (f) voltage rating (v) temperature coefficient size (l w h) (mm) package murata grm155r60j225me95 2.2 6.3 x5r 1.0 0.5 0.5 0402 taiyo yuden jmk105bj225mv-f 2.2 6.3 x5r 1.0 0.5 0.5 0402 tdk c1005x5r0j225m 2.2 6.3 x5r 1.0 0.5 0.5 0402 table 7. output capacitor selection manufacturer part numbers capacitance (f) voltage rating (v) temperature coefficient size (l w h) (mm) package murata grm155r60j475me87 4.7 6.3 x5r 1.0 0.5 0.5 0402 grm155r60g475me47 4.7 4 x5r 1.0 0.5 0.5 0402 taiyo yuden amk105bj475mv-f 4.7 4 x5r 1.0 0.5 0.5 0402 tdk c1005x5r0j475m 4.7 6.3 x5r 1.0 0.5 0.5 0402
adp2125 rev. 0 | page 13 of 16 output capacitor selection the output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. for a given loop crossover frequency (the frequency at which the loop gain drops to 0 db), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. when choosing output capacitors, it is also important to account for the loss of capacitance due to output voltage dc bias. this may result in using a capacitor with a higher rated voltage to achieve the desired capacitance value. additionally, if ceramic output capacitors are used, the capacitor rms ripple current rating should always meet the application requirements. the rms ripple current is calculated as follows: () ( ) )( )( 32 1 max in sw out max in out cout rms vfl vvv i ? = (5) at nominal load currents, the converter operates in forced pwm mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charging and discharging the output capacitor. v out = i l ( esr + 1/(8 c out f sw )) (6) the largest voltage ripple occurs at the highest input voltage. the adp2125 is designed to operate with small 4.7 f ceramic capacitors that have low esr and esl. these components are therefore able to meet tight output voltage ripple specifications. x5r or x7r dielectrics with a voltage rating of 4 v or higher are recommended. thermal limit calculations the operating junction temperature (t j ) of the device is dependent on the ambient operating temperature (t a ) of the application, the power dissipation of the adp2125 (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). the operating junction temperature (t j ) is calculated using the following equation: t j = t a + ( p d ja ) (7) where ja is 120c/w, as provided in table 3 . the adp2125 can be damaged when the operating junction temperature limits are exceeded. monitoring ambient tempera- ture does not guarantee that the junction temperature (t j ) is within the specified temperature limits. ? in applications with high p d and poor pcb thermal resistance, the maximum ambient temperature may need to be derated. ? in applications with moderate p d and good pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the power dissipation (p d ) of the adp2125 is only a portion of the power loss of the overall application. for a given application with known operating conditions, the application power loss can be calculated by combinin g the following equations for power loss (p loss ) and efficiency (): p loss = p in ? p out (8) 100 = in out p p (9) the resulting equation uses the output power and the efficiency to determine the p loss . ? ? ? ? ? ? ? ? ? = 1 100 out loss pp (10) the power loss calculated using th is approach is the combined loss of the adp2125 device (p d ), the inductor (p l ), input capacitor (p cin ), and the output capacitor (p cout ), as shown in the following equation: p loss = p d + p l + p cin + p cout (11) the power loss for the inductor, input capacitor, and output capacitor can be calculated as follows: p l = i rms 2 dcr (12) cin rms cin esr i p ? ? ? ? ? ? = 2 2 (13) p cout = ( iout ) 2 esr cout (14) if multilayer chip capacitors with low esr are used, the power loss in the input and output capacitors is negligible and p d + p l >> p cin + p cout (15) p loss p d + p l (16) the final equation for calculating p d can be used in equation 7 to ensure that the operating junction temperature is not exceeded. l out l loss d p pppp ? ? ? ? ? ? ? ? ? ? ? 1 100 (17)
adp2125 rev. 0 | page 14 of 16 pcb layout guidelines 08774-022 figure 22. adp2125 recommended top layer layout 08774-023 figure 23. adp2125 recommended bottom layer layout for high efficiency, good regulation, and stability, a well- designed and manufactured pcb is required. use the following guidelines when designing pcbs: ? keep the low esr input capacitor, c in , close to vin and gnd. ? keep high current traces as short and as wide as possible. ? avoid routing high impedance traces near any node con- nected to sw or near the inductor to prevent radiated noise injection. ? keep the low esr output capacitor, c out , close to the fb and gnd pins of the adp2125. long trace lengths from the part to the output capacitor add series inductance that may cause instability or increased ripple. to ensure package reliability, consider the following guidelines when designing the footprint for the adp2125. the bumped_chip device footprint must ultimately be determined according to application and customer specific reliability requirements, pcb fabrication quality, and pcb assembly capabilities. ? the cu pad on the pcb for each solder bump should be 80% to 100% of the width of the solder bump. a smaller pad opening favors solder joint reliability (sjr) perfor- mance, whereas a larger pad opening favors drop test performance. the maximum pad size, including tolerance, should not exceed 180 m. ? electroplated nickel, immersion gold (enig) and organic solderability preservative (osp) were used for internal reliability testing and are recommended. ? nonsolder mask defined (nsmd) cu pads are recom- mended for bumped_chip packages. ? the solder mask opening should be approximately 100 m larger than the pad opening. ? the trace width should be less than two-thirds the size of the pad opening. ? the routing of traces from the cu pads should be symmet- rical in x and y directions. symmetrical routing of the traces prevents part rotation due to uneven solder wetting/surface tension forces. ? stencil design is important for proper transfer of paste onto the cu pads. area ratio (ar), the relationship between the surface area of the stencil aperture and the inside surface area of the aperture walls, is critically important. stencil thickness has the greatest impact on this ratio. ar values from 0.66 to 0.8 provide the best paste transfer efficiency and repeatability. the ar is calculated using the following equation: a w ap ar = where: ap is the area of the aperture opening. aw is the wall area.
adp2125 rev. 0 | page 15 of 16 outline dimensions 082409-a 0.40 bsc 0.115 typ 0.170 typ 0.80 bsc 1.340 1.300 1.260 0.940 0.900 0.860 seating plane 0.405 0.390 0.375 0.40 bsc a 12 b c top view (ball side down) bottom view (ball side up) ball a1 identifier 0.05 nom coplanarity figure 24. 6-ball bumped ba re die sales [bumped_chip] (cd-6-2) dimensions shown in millimeters 08774-008 direction of feed figure 25. tape and reel orientation for adp2125 ordering guide model 1 output voltage pin a1 function temperature range package description package option 2 branding adp2125bcdz-1.26r7 1.26 v nc ?40c to +85c 6-ball bumped bare die [bumped_chip] cd-6-2 lep 1 z = rohs compliant part. 2 this package option is halide free.
adp2125 rev. 0 | page 16 of 16 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08774-0-9/10(0)

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